| Server IP : 127.0.1.1 / Your IP : 216.73.216.172 Web Server : Apache/2.4.52 (Ubuntu) System : Linux bahcrestlinepropertiesllc 5.15.0-113-generic #123-Ubuntu SMP Mon Jun 10 08:16:17 UTC 2024 x86_64 User : www-data ( 33) PHP Version : 7.4.33 Disable Function : pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wifcontinued,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_get_handler,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority,pcntl_async_signals,pcntl_unshare, MySQL : OFF | cURL : ON | WGET : ON | Perl : ON | Python : OFF | Sudo : ON | Pkexec : ON Directory : /proc/1648833/cwd/lib/modules/5.15.0-153-generic/build/include/dt-bindings/clock/ |
Upload File : |
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2014 Ulrich Hecht */ #ifndef __DT_BINDINGS_CLOCK_R8A7740_H__ #define __DT_BINDINGS_CLOCK_R8A7740_H__ /* CPG */ #define R8A7740_CLK_SYSTEM 0 #define R8A7740_CLK_PLLC0 1 #define R8A7740_CLK_PLLC1 2 #define R8A7740_CLK_PLLC2 3 #define R8A7740_CLK_R 4 #define R8A7740_CLK_USB24S 5 #define R8A7740_CLK_I 6 #define R8A7740_CLK_ZG 7 #define R8A7740_CLK_B 8 #define R8A7740_CLK_M1 9 #define R8A7740_CLK_HP 10 #define R8A7740_CLK_HPP 11 #define R8A7740_CLK_USBP 12 #define R8A7740_CLK_S 13 #define R8A7740_CLK_ZB 14 #define R8A7740_CLK_M3 15 #define R8A7740_CLK_CP 16 /* MSTP1 */ #define R8A7740_CLK_CEU21 28 #define R8A7740_CLK_CEU20 27 #define R8A7740_CLK_TMU0 25 #define R8A7740_CLK_LCDC1 17 #define R8A7740_CLK_IIC0 16 #define R8A7740_CLK_TMU1 11 #define R8A7740_CLK_LCDC0 0 /* MSTP2 */ #define R8A7740_CLK_SCIFA6 30 #define R8A7740_CLK_INTCA 29 #define R8A7740_CLK_SCIFA7 22 #define R8A7740_CLK_DMAC1 18 #define R8A7740_CLK_DMAC2 17 #define R8A7740_CLK_DMAC3 16 #define R8A7740_CLK_USBDMAC 14 #define R8A7740_CLK_SCIFA5 7 #define R8A7740_CLK_SCIFB 6 #define R8A7740_CLK_SCIFA0 4 #define R8A7740_CLK_SCIFA1 3 #define R8A7740_CLK_SCIFA2 2 #define R8A7740_CLK_SCIFA3 1 #define R8A7740_CLK_SCIFA4 0 /* MSTP3 */ #define R8A7740_CLK_CMT1 29 #define R8A7740_CLK_FSI 28 #define R8A7740_CLK_IIC1 23 #define R8A7740_CLK_USBF 20 #define R8A7740_CLK_SDHI0 14 #define R8A7740_CLK_SDHI1 13 #define R8A7740_CLK_MMC 12 #define R8A7740_CLK_GETHER 9 #define R8A7740_CLK_TPU0 4 /* MSTP4 */ #define R8A7740_CLK_USBH 16 #define R8A7740_CLK_SDHI2 15 #define R8A7740_CLK_USBFUNC 7 #define R8A7740_CLK_USBPHY 6 /* SUBCK* */ #define R8A7740_CLK_SUBCK 9 #define R8A7740_CLK_SUBCK2 10 #endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */